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1 ltc1416 low power 14-bit, 400ksps sampling adc u a o pp l ic at i ty p i ca l complete, 70mw, 14-bit adc with 80.5db s/(n + d) busy cs convst rd shdn 14-bit adc 14 s/h buffer 4k ltc1416 ? ? d13 (msb) d0 (lsb) ?v v ss a in + a in v ref refcomp dv dd av dd 1 f 22 f 10 f 10 f agnd 1416 ta01 dgnd 2.5v reference timing and logic output buffers input frequency (hz) 1k effective bits signal/(noise + distortion) (db) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 86 80 74 68 62 10k 100k 1416 ta02 1m 2m f sample = 400khz nyquist frequency effective bits and signal-to-(noise + distortion) vs input frequency s f ea t u re n sample rate: 400ksps n power dissipation: 70mw n guaranteed 1.5lsb dnl, 2lsb inl (max) n 80.5db s/(n + d) and 93db thd at 100khz n 80db s/(n + d) and 90db thd at nyquist n nap and sleep shutdown modes n operates with internal or external reference n true differential inputs reject common mode noise n 15mhz full power bandwidth sampling n 2.5v bipolar input range n 28-pin ssop package u s a o pp l ic at i , ltc and lt are registered trademarks of linear technology corporation. n telecommunications n digital signal processing n multiplexed data acquisition systems n high speed data acquisition n spectrum analysis n imaging systems the ltc ? 1416 is a 2.2 m s, 400ksps, 14-bit sampling a/d converter that draws only 70mw from 5v supplies. this easy-to-use device includes a high dynamic range sample- and-hold and a precision reference. two digitally select- able power shutdown modes provide flexibility for low power systems. the ltc1416s full-scale input range is 2.5v. maximum dc specifications include 2lsb inl, 1.5lsb dnl over temperature. outstanding ac performance includes 80.5db s/(n + d) and 93db thd with a 100khz input, and 80db s/(n + d) and 90db thd at the nyquist input frequency of 200khz. the unique differential input sample-and-hold can ac- quire single-ended or differential input signals up to its 15mhz bandwidth. the 60db common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. the adc has a m p compatible, 14-bit parallel output port. there is no pipeline delay in the conversion results. a separate convert start input and a data ready signal (busy) ease connections to fifos, dsps and micropro- cessors. d u escriptio
2 ltc1416 av dd = dv dd = v dd (notes 1, 2) supply voltage (v dd ) ................................................ 6v negative supply voltage (v ss )................................ C 6v total supply voltage (v dd to v ss ) .......................... 12v analog input voltage (note 3) ......................... (v ss C 0.3v) to (v dd + 0.3v) digital input voltage (note 4) .......... (v ss C 0.3v) to 10v digital output voltage ....... (v ss C 0.3v) to (v dd + 0.3v) power dissipation ............................................. 500mw operating temperature range commercial ............................................ 0 c to 70 c industrial ........................................... C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c a u g w a w u w a r b s o lu t exi t i s wu u package / o rder i for atio order part number ltc1416cg LTC1416IG t jmax = 110 c, q ja = 95 c/w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a in + a in v ref refcomp agnd d13(msb) d12 d11 d10 d9 d8 d7 d6 dgnd av dd dv dd v ss busy cs convst rd shdn d0 d1 d2 d3 d4 d5 g package 28-lead plastic ssop top view consult factory for military grade parts and for a grade parts. symbol parameter conditions min typ max units v in analog input range (note 9) 4.75v v dd 5.25v, C 5.25v v ss C 4.75v l 2.5 v i in analog input leakage current cs = high l 1 m a c in analog input capacitance between conversions 15 pf during conversions 5 pf t acq sample-and-hold acquisition time (note 9) l 100 400 ns t ap sample-and-hold aperture delay time C1.5 ns t jitter sample-and-hold aperture delay time jitter 2 ps rms cmrr analog input common mode rejection ratio C 2.5v < (a in C = a in + ) < 2.5v 60 db (note 5) put u i a a u log cc hara terist ics co u verter with internal reference (notes 5, 6) parameter conditions min typ max units resolution (no missing codes) l 13 bits integral linearity error (note 7) l 0.8 2 lsb differential linearity error l 0.7 1.5 lsb offset error (note 8) l 5 20 lsb full-scale error internal reference 20 60 lsb external reference = 2.5v 10 40 lsb full-scale tempco i out(ref) = 0 15 ppm/ c
3 ltc1416 symbol parameter conditions min typ max units s/(n + d) signal-to-(noise + distortion) ratio 100khz input signal l 77 80.5 db 200khz input signal 80 db thd total harmonic distortion 100khz input signal, first 5 harmonics l C 93 C 86 db 200khz input signal, first 5 harmonics C 90 db sfdr spurious-free dynamic range 100khz input signal l C 95 C 86 db imd intermodulation distortion f in1 = 87.01172khz, f in2 = 113.18359khz C 90 db full power bandwidth 15 mhz full linear bandwidth (s/(n + d) 3 77db) 0.8 mhz symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v l 2.4 v v il low level input voltage v dd = 4.75v l 0.8 v i in digital input current v in = 0v to v dd l 10 m a c in digital input capacitance 5pf v oh high level output voltage v dd = 4.75v i out = C 10 m a 4.5 v i out = C 200 m a l 4.0 v v ol low level output voltage v dd = 4.75v i out = 160 m a 0.05 v i out = 1.6ma l 0.10 0.4 v i oz hi-z output leakage d13 to d0 v out = 0v to v dd , cs high l 10 m a c oz hi-z output capacitance d13 to d0 cs high (note 9 ) l 15 pf i source output source current v out = 0v C 10 ma i sink output sink current v out = v dd 10 ma parameter conditions min typ max units v ref output voltage i out = 0 2.480 2.500 2.520 v v ref output tempco i out = 0 15 ppm/ c v ref line regulation 4.75v v dd 5.25v 0.05 lsb/v C 5.25v v ss C 4.75v 0.05 lsb/v v ref output resistance C 0.1ma ? i out ? 0.1ma 4 k w comp output voltage i out = 0 4.06 v symbol parameter conditions min typ max units v dd positive supply voltage (note 10) 4.75 5.25 v v ss negative supply voltage (note 10) C 4.75 C 5.25 v i dd positive supply current l 710 ma nap mode shdn = 0v, cs = 0v 0.8 1.2 ma sleep mode shdn = 0v, cs = 5v 1 m a i ss negative supply current l 710 ma nap mode shdn = 0v, cs = 0v 20 m a sleep mode shdn = 0v, cs = 5v 15 m a i ter al refere ce characteristics u u u dy a ic accuracy u w (note 5) (note 5) digital i puts a d digital outputs u u (note 5) power require e ts w u (note 5)
4 ltc1416 symbol parameter conditions min typ max units power require e ts w u (note 5) p diss power dissipation l 70 100 mw power dissipation, nap mode shdn = 0v, cs = 0v 4 6 mw power dissipation, sleep mode shdn = 0v, cs = 5v 0.1 mw note 6: linearity, offset and full-scale specifications apply for a single- ended a in + input with a in C grounded. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: bipolar offset is the offset voltage measured from C 0.5lsb when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. note 9: guaranteed by design, not subject to test. note 10: recommended operating conditions. note 11: the falling convst edge starts a conversion. if convst returns high at a critical point during the conversion it can create small errors. for best results ensure that convst returns high either within 900ns after the start of the conversion or after busy rises. symbol parameter conditions min typ max units f sample(max) maximum sampling frequency l 400 khz t conv conversion time l 1.5 1.9 2.2 m s t acq acquisition time (note 9) l 100 400 ns t acq+conv acquisition + conversion time l 2 2.5 m s t 1 cs to rd setup time (notes 9, 10) l 0ns t 2 cs to convst setup time (notes 9, 10) l 10 ns t 3 cs to shdn setup time (notes 9, 10) l 10 ns t 4 shdn - to convst wake-up time (note 10) 400 ns t 5 convst low time (notes 10, 11) l 40 ns t 6 convst to busy delay c l = 25pf 25 ns l 50 ns t 7 data ready before busy - 75 100 ns l 50 ns t 8 delay between conversions (note 10) l 40 ns t 9 wait time rd after busy - l C5 ns t 10 data access time after rd c l = 25pf 15 25 ns l 35 ns c l = 100pf 20 35 ns l 50 ns t 11 bus relinquish time 820 ns 0 c t a 70 c l 25 ns C40 c t a 85 c l 30 ns t 12 rd low time l t 10 ns t 13 convst high time l 40 ns (note 5, see figures 15 to 21) ti i g characteristics w u the l denotes specifications which apply over the full operating temperature range; all other limits and typicals at t a = 25 c. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd and agnd wired together unless otherwise noted. note 3: when these pin voltages are taken below v ss or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below v ss or above v dd without latchup. note 4: when these pin voltages are taken below v ss , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below v ss without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, v ss = C 5v, f sample = 400khz, t r = t f = 5ns unless otherwise specified.
5 ltc1416 typical perfor m a n ce characteristics uw distortion vs input frequency differential nonlinearity vs output code input common mode rejection vs input frequency input frequency (hz) 1k signal/(noise + distortion) (db) 90 80 70 60 50 40 30 20 10 0 10k 100k 1416 g01 1m 2m v in = 0db v in = 20db v in = 60db s/(n + d) vs input frequency and amplitude input frequency (hz) 1k spurious-free dynamic range (db) 0 10 20 30 40 50 60 70 80 90 100 10k 100k 1416 g04 1m 2m spurious-free dynamic range vs input frequency output code 0 dnl error (lsb) 16384 v out = 2.5v v ref = 2.5v 1416 g06 4096 8192 12288 1.0 0.5 0 0.5 1.0 output code 0 inl error (lsb) 16384 v out = 2.5v v ref = 2.5v 1416 g07 4096 8192 12288 1.0 0.5 0 0.5 1.0 integral nonlinearity vs output code input frequency (hz) 1k common mode rejection (db) 80 70 60 50 40 30 20 10 0 10k 100k 1416 g09 1m 2m input frequency (hz) 1k amplitude (db below the fundamental) 0 10 20 30 40 50 60 70 80 90 100 110 10k 100k 1416 g03 1m 2m thd 2nd 3rd signal-to-noise ratio vs input frequency intermodulation distortion plot power supply feedthrough vs ripple frequency input frequency (hz) 1k signal-to-noise ratio (db) 90 80 70 60 50 40 30 20 10 0 10k 100k 1416 g02 1m 2m frequency (hz) 0 amplitude (db) 0 20 40 60 80 100 120 140 20 100 140 1416 g05 80 180 200 40 60 120 160 f sample = 400khz f a =87.01171876khz f b =113.1835938khz ripple frequency (hz) 1k amplitude of power supply feedthrough (db) 0 10 20 30 40 50 60 70 80 90 100 10k 100k 1416 g08 1m 2m dgnd (v in = 100mv) v ss (v in = 10mv) v dd (v in = 10mv)
6 ltc1416 pi fu ctio s uu u a in + (pin 1): 2.5v positive analog input. a in C (pin 2): 2.5v negative analog input. v ref (pin 3): 2.5v reference output. bypass to agnd with 1 m f. refcomp (pin 4): 4.06v reference output. bypass to agnd with 22 m f tantalum in parallel with 0.1 m f ceramic, or 22 m f ceramic. agnd (pin 5): analog ground. d13 to d6 (pins 6 to 13): three-state data outputs. dgnd (pin 14): digital ground for internal logic. tie to agnd. d5 to d0 (pins 15 to 20): three-state data outputs. shdn (pin 21): power shutdown input. low selects shutdown. shutdown mode selected by cs. cs = 0 for nap mode and cs = 1 for sleep mode. rd (pin 22): read input. this enables the output drivers when cs is low. fu ctio al block diagra uu w convst (pin 23): conversion start signal. this active low signal starts a conversion on its falling edge. cs (pin 24): the chip select input must be low for the adc to recognize convst and rd inputs. cs also sets the shutdown mode when shdn goes low. cs and shdn low select the quick wake-up nap mode. cs high and shdn low select sleep mode. busy (pin 25): the busy output shows the converter status. it is low when a conversion is in progress. data is valid on the rising edge of busy. v ss (pin 26): C 5v negative supply. bypass to agnd with 10 m f tantalum in parallel with 0.1 m f ceramic, or 10 m f ceramic. dv dd (pin 27): 5v positive supply. tie to pin 28. av dd (pin 28): 5v positive supply. bypass to agnd with 10 m f tantalum in parallel with 0.1 m f ceramic, or 10 m f ceramic. 14-bit capacitive dac comp ref amp 2.5v ref 4k refcomp (4.06v) c sample c sample ? ? d13 d0 busy control logic cs convst rd shdn internal clock zeroing switches dv dd v ss av dd a in + a in v ref agnd dgnd 14 1416 bd + successive approximation register output latches
7 ltc1416 test circuits 1k c l c l dbn (a) hi-z to v oh and v ol to v oh (b) hi-z to v ol and v oh to v ol dbn 1k 5v 1416 tc01 load circuits for access timing load circuits for output float delay 1k 100pf 100pf dbn (a) v oh to hi-z (b) v ol to hi-z dbn 1k 5v 1416 tc02 applicatio n s i n for m atio n wu u u conversion details the ltc1416 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit parallel output. the adc is complete with a precision reference and an internal clock. the control logic provides easy interface to microproces- sors and dsps. (please refer to the digital interface section for the data format.) conversion start is controlled by the cs and convst inputs. at the start of the conversion the successive approximation register (sar) is reset. once a conversion cycle has begun, it cannot be restarted. during the conversion, the internal differential 14-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). referring to figure 1, the a in + and a in C inputs are connected to the sample-and-hold capacitors (c sample ) during the acquire phase and the comparator offset is nulled by the zeroing switches. in this acquire phase, a minimum delay of 400ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. during the convert phase the comparator zeroing switches open, putting the comparator into compare mode. the input switches connect the c sample capacitors to ground, transferring the differential analog input charge onto the summing junction. this input charge is successively com- pared with the binary-weighted charges supplied by the differential capacitive dac. bit decisions are made by the high speed comparator. at the end of a conversion, the differential dac output balances the a in + and a in C input charges. the sar contents (a 14-bit data word) which represents the difference of a in + and a in C are loaded into the 14-bit output latches. sample sample c sample + c sample v dac v dac + ? ? d13 d0 zeroing switches a in + c dac + c dac a in 14 1416 f01 comp + hold hold hold hold output latch sar figure 1. simplified block diagram
8 ltc1416 applicatio n s i n for m atio n wu u u figure 3. effective bits and signal/(noise + distortion) vs input frequency dynamic performance the ltc1416 has excellent high speed sampling capabil- ity. fft (fast fourier transform) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algo- rithm, the adcs spectral content can be examined for frequencies outside the fundamental. figure 2 shows a typical ltc1416 fft plot. signal-to-noise ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 2a shows a typical spectral content with a 400khz sampling rate and a 100khz input. the dynamic performance is excellent for input frequencies up to and beyond the nyquist limit of 200khz, figure 2b. effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to the s/(n + d) by the equation: enob = [s/(n + d) C 1.76]/6.02 where enob is the effective number of bits of resolution and s/(n + d) is expressed in db. at the maximum sampling rate of 400khz the ltc1416 maintains near ideal enobs up to the nyquist input frequency of 200khz (refer to figure 3). frequency (khz) 0 amplitude (db)) 150 1416 f02a 50 100 200 0 20 40 60 80 100 120 140 25 75 125 175 f sample = 400khz f in = 101.5625khz sfdr = 95.2db sinad = 80.5db frequency (khz) 0 amplitude (db)) 150 1416 f02b 50 100 200 0 20 40 60 80 100 120 140 25 75 125 175 f sample = 400khz f in = 189.9414khz sfdr = 94.8db sinad = 80.2db input frequency (hz) 1k effective bits signal/(noise + distortion) (db) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 86 80 74 68 62 10k 100k 1416 ta02 1m 2m f sample = 400khz nyquist frequency figure 2a. ltc1416 nonaveraged, 4096 point fft, input frequency = 100khz figure 2b. ltc1416 nonaveraged, 4096 point fft, input frequency = 190khz
9 ltc1416 applicatio n s i n for m atio n wu u u ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (fa + fb). if the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order imd products can be expressed by the following formula: imd fa fb + () = () 20 log amplitude at fa + fb amplitude at fa total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd vv vn v = +++ 20 log v2 2 34 1 22 2 ... where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. thd versus input fre- quency is shown in figure 4. the ltc1416 has good distortion performance up to the nyquist frequency and beyond. input frequency (hz) 1k amplitude (db below the fundamental) 0 10 20 30 40 50 60 70 80 90 100 110 10k 100k 1416 g03 1m 2m thd 2nd 3rd figure 4. distortion vs input frequency intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- frequency (hz) 0 amplitude (db) 0 20 40 60 80 100 120 140 20 100 140 1416 g05 80 180 200 40 60 120 160 f sample = 400khz f a =87.01171876khz f b =113.1835938khz figure 5. intermodulation distortion plot peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full-scale input signal. full-power and full-linear bandwidth the full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input signal. the full-linear bandwidth is the input frequency at which the s/(n + d) has dropped to 77db (12.5 effective bits). the ltc1416 has been designed to optimize input bandwidth, allowing the adc to undersample input signals with frequencies above the converters nyquist frequency. the noise floor stays very low at high frequencies; s/(n + d) becomes dominated by distortion at frequencies far beyond nyquist.
10 ltc1416 applicatio n s i n for m atio n wu u u driving the analog input the differential analog inputs of the ltc1416 are easy to drive. the inputs may be driven differentially or as a single- ended input (i.e., the a in C input is grounded). the a in + and a in C inputs are sampled at the same instant. any un- wanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample- and-hold circuit. the inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. during conversion the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low, then the ltc1416 inputs can be driven directly. as source impedance increases so will acquisition time (see figure 6). for minimum acquisition time, with high source impedance, a buffer amplifier should be used. the only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 400ns for full throughput rate). frequency. for example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 50mhz, then the output impedance at 50mhz should be less than 100 w . the second requirement is that the closed-loop bandwidth must be greater than 10mhz to ensure adequate small- signal settling for full throughput rate. if slower op amps are used, more settling time can be provided by increasing the time between conversions. the best choice for an op amp to drive ltc1416 will depend on the application. generally, applications fall into two categories: ac applications where dynamic specifica- tions are most critical and time domain applications where dc accuracy and settling time are most critical. the following list is a summary of the op amps that are suitable for driving the ltc1416. more detailed information is available in the linear technology databooks and the linearview tm cd-rom. lt ? 1220: 30mhz unity-gain bandwidth voltage feedback amplifier. 5v to 15v supplies, excellent dc specifica- tions. lt1223: 100mhz video current feedback amplifier. 6ma supply current, 5v to 15v supplies, low distortion at frequencies above 400khz, low noise, good for ac appli- cations. lt1227: 140mhz video current feedback amplifier. 10ma supply current, 5v to 15v supplies, lowest distortion at frequencies above 400khz, low noise, best for ac applica- tions. lt1229/lt1230: dual and quad 100mhz current feedback amplifiers. 2v to 15v supplies, low noise, good ac specs, 6ma supply current each amplifier. lt1360: 50mhz voltage feedback amplifier. 3.8ma supply current, good ac and dc specs, 5v to 15v supplies. lt1363: 70mhz, 1000v/ m s op amps. 6.3ma supply cur- rent, good ac and dc specs. lt1364/lt1365: dual and quad 70mhz, 100v/ m s op amps. 6.3ma supply current per amplifier. linearview is a trademark of linear technology corporation. source resistance ( w ) acquisition time ( m s) 10 1k 10k 100k 1416 f06 100 10 1 0.1 0.01 figure 6. acquisition time vs source resistance choosing an input amplifier choosing an input amplifier is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<100 w ) at the closed-loop bandwidth
11 ltc1416 applicatio n s i n for m atio n wu u u input filtering the noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the ltc1416 noise and distortion. the small-signal band- width of the sample-and-hold circuit is 15mhz. any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. noisy input circuitry should be filtered prior to the analog inputs to minimize noise. a simple 1-pole rc filter is sufficient for many applications. for example, figure 7 shows a 1000pf capacitor from a in + to ground and a 200 w source resistor to limit the input bandwidth to 800khz. the 1000pf capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the adc input from sam- pling glitch sensitive circuitry. high quality capacitors and resistors should be used since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can also generate distortion from self-heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. accommodate other input ranges often with little or no additional circuitry. the following sections describe the reference and input circuitry and how they affect the input range. internal reference the ltc1416 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500v. it is connected internally to a reference amplifier and is available at v ref (pin 3). see figure 8a. a 4k resistor is in series with the output so that it can be easily overdriven by an external reference or other cir- cuitry (see figure 8b). the reference amplifier gains the voltage at the v ref pin by 1.625 to create the required internal reference voltage. this provides buffering be- tween the v ref pin and the high speed capacitive dac. the v ref refcomp agnd 2.5v 4.0625v 3 4 5 22 f 1416 f08a r1 4k r2 80k bandgap reference ltc1416 ref amp r3 128k figure 8a. ltc1416 reference circuit 1 2 3 22 m f analog input 1416 f08b a in + a in v ref ltc1416 refcomp agnd 4 5 5v lt1019a-2.5 v out v in figure 8b. using the lt1019-2.5 as an external reference 1 2 3 1000pf 200 22 m f analog input 1416 f07 a in + a in v ref ltc1416 refcomp agnd 4 5 figure 7. rc input filter input range the 2.5v input range of the ltc1416 is optimized for low noise and low distortion. most op amps also perform best over this same range, allowing direct coupling to the analog inputs and eliminating the need for special transla- tion circuitry. some applications may require other input ranges. the ltc1416 differential inputs and reference circuitry can
12 ltc1416 applicatio n s i n for m atio n wu u u reference amplifier compensation pin, refcomp (pin 4), must be bypassed with a capacitor to ground. the refer- ence amplifier is stable with capacitors of 1 m f or greater. for the best noise performance, a 22 m f ceramic or 22 m f tantalum in parallel with a 0.1 m f ceramic is recommended. the v ref pin can be driven with a dac or other means shown in figure 9. this is useful in applications where the peak input signal amplitude may vary. the input span of the adc can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. the filtering of the internal ltc1416 reference amplifier will limit the bandwidth and settling time of this circuit. a settling time of 5ms should be allowed for after a reference adjustment. input frequency (hz) 1k common mode rejection (db) 80 70 60 50 40 30 20 10 0 10k 100k 1416 g09 1m 2m figure 10a. cmrr vs input frequency 1 2 22 m f analog input 1416 f10b a in + a in ltc1416 refcomp agnd 4 5 3 0v to 5v 2.5v v ref converts a 0v to 5v analog input signal with no additional translation circuitry. full-scale and offset adjustment figure 11a shows the ideal input/output characteristics for the ltc1416. the code transitions occur midway between successive integer lsb values (i.e., C fs + 0.5lsb, C fs + 1.5lsb, C fs + 2.5lsb, . . . fs C 1.5lsb, fs C 0.5lsb). the output is twos complement binary with 1lsb = fs C (C fs)/16384 = 5v/16384 = 305.2 m v. in applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. offset error must be adjusted before full-scale error. figure 11b shows the extra components required for full-scale error adjustment. zero offset is achieved by adjusting the offset applied to the a in C input. for zero offset error, apply C 152 m v (i.e., C 0.5lsb) at a in + and adjust the offset at the a in C input until the output code flickers between 0000 figure 10b. selectable 0v to 5v or 2.5v input range 1 2 3 22 m f analog input 1.25v to 3v 1416 f09 a in + a in v ref ltc1416 ltc1450 refcomp agnd 4 5 figure 9. driving v ref with a dac differential inputs the ltc1416 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. the adc will always convert the difference of a in + C a in C independent of the common mode voltage. the common mode rejection holds up to extremely high frequencies (see figure 10a). the only requirement is that both inputs cannot exceed the av dd or av ss power supply voltages. integral nonlinearity errors (inl) and differential nonlinearity errors (dnl) are independent of the common mode voltage, however, the bipolar zero error (bze) will vary. the change in bze is typically less than 0.1% of the common mode voltage. dynamic performance is also affected by the common mode voltage. thd will degrade as the inputs approach either power supply rail, from 90db with a common mode of 0v to 79db with a common mode of 2.5v or C 2.5v. differential inputs allow greater flexibility for accepting different input ranges. figure 10b shows a circuit that
13 ltc1416 applicatio n s i n for m atio n wu u u 0000 0000 00 and 1111 1111 1111 11. for full-scale adjustment, an input voltage of 2.499544v (fs/2 C 1.5lsb) is applied to a in and r2 is adjusted until the output code flickers between 0111 1111 1111 10 and 0111 1111 1111 11. applications, however, do not have a C5v supply readily available and most adcs have inadequate psrr to suffi- ciently attenuate the noise created by a switching or charge pump supply. the ltc1416s excellent psrr makes it possible to achieve good performance, even at 14 bits, using a switch based regulator for a C5v supply. figure 12a shows a circuit using an lt1373 configured as a cuk converter creating C5v from a 5v supply. the circuit shown in figure 12b uses an lt1054 regulated charge pump to provide C5v. this circuit has the advantage of reduced board space and fewer passive components. (for further details refer to linear technology magazine, june 1997, page 29.) board layout and bypassing wire wrap boards are not recommended for high resolu- tion or high speed a/d converters. to obtain the best performance from the ltc1416, a printed circuit board with ground plane is required. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. the analog input should be screened by agnd. an analog ground plane separate from the logic system ground should be established under and around the adc (see figure 13). pin 5 (agnd), pins 14 and 19 (adcs dgnd) and all other analog grounds should be connected to this single analog ground point. the refcomp bypass capacitor and the dv dd bypass capacitor should also be connected to this analog ground plane. no other digital grounds should be connected to this analog ground plane. low impedance analog and digital power supply common returns are essential to low noise operation of the adc and the foil width for these tracks should be as wide as possible. in applications where the adc data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. these errors are due to feedthrough from the microprocessor to the successive approximation comparator. the problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the adc data bus. the 1416 f11a 011...111 011...110 000...001 000...000 111...111 111...110 100...001 100...000 fs ?1lsb (fs ?1lsb) input voltage (a in + ?a in ) output code figure 11a. ltc1416 transfer characteristics analog input 1416 f11b 1 2 3 r4 100 w r2 50k r3 24k ?v r6 24k r1 50k r5 47k 4 5 22 m f a in + a in v ref refcomp agnd ltc1416 figure 11b. offset and full-scale adjust circuit generating a C 5v supply there are several advantages to using 5v supplies rather than a single 5v supply. a larger signal magnitude is possible which increases the dynamic range and improves the signal-to-noise ratio. operating on 5v supplies also offers increased headroom which eases the requirements for signal conditioning circuitry, avoids the limitations of rail-to-rail operation and widens the selec- tion of high performance operational amplifiers. some
14 ltc1416 applicatio n s i n for m atio n wu u u figure 12b. using the lt1054 to generate a C 5v supply + + 28 1 27 2 26 3 25 4 24 c7 1 m f cer c5 c6 5v ?v analog input ltc1416 5 23 6 22 microprocessor/ microcontroller interface 7 21 8 20 9 19 10 18 11 17 12 16 13 15 14 c1 10 m f tant v + fb/shdn 1 v ref 6 osc 7 8 cap + 2 gnd 3 v out 5 cap 4 u1 lt1054 r2, 120k r1, 30.1k c3 0.002 m f c4 100 m f tant c2 2 m f c5 = 22 m f ceramic c6, c7 = 10 m f ceramic busy cs convst rd shdn d0 d1 d2 d3 d4 d5 av dd dv dd v ss comp agnd d13 (msb) d12 d11 d10 d9 d8 d7 d6 dgnd a in + a in v ref 1416 f12b + + av dd 28 1 dv dd 27 2 v ss 26 3 busy 25 4 cs 24 c7 1 m f cer c5 c8 22 m f 10v tant c6 5v ?v 1416 f12a analog input ltc1416 5 convst 23 6 rd 22 microprocessor/ microcontroller interface 7 shdn 21 8 d0 20 9 d1 19 10 d2 18 11 d3 17 12 d4 16 13 d5 15 a in + a in v ref comp agnd d13 (msb) d12 d11 d10 d9 d8 d7 d6 dgnd 14 v sw 1 2 4 3 l1 v in 5 nfb 3 8 s/s 4 gnd 7 v c c9 0.01 m f d1 r3 4.99k r5 4.99k 1% r6 499 w 1% r4 4.99k 1% c11 100 m f 10v tant c12 0.1 m f 1 gnd s 6 u2 lt1373 c10 10 m f cer cuk* converter c5 = 22 m f ceramic c6, c7 = 10 m f ceramic l1 = octapac ctx-100-1 d1 = 1n5818 figure 12a. using the lt1373 to generate a C 5v supply
15 ltc1416 applicatio n s i n for m atio n wu u u figure 13. power supply grounding practice. traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the ltc1416 has differential inputs to minimize noise coupling. common mode noise on the a in + and a in C leads will be rejected by the input cmrr. the a in C input can be used as a ground sense for the a in + input; the ltc1416 will hold and convert the difference voltage between a in + and a in C . the leads to a in + (pin 1) and a in C (pin 2) should be kept as short as possible. in applications where this is not possible, the a in + and a in C traces should be run side by side to equalize coupling. supply bypassing high quality, low series resistance ceramic, bypass capacitors should be used at the v dd (10 m f) and refcomp (22 m f) pins as shown in the typical application on the first page of this data sheet. surface mount ceramic capacitors such as murata grm235y5v106z016 provide excellent bypassing in a small board space. alternatively tantalum capacitors in parallel with 0.1 m f ceramic capacitors can be used. bypass capacitors must be located as close to the pins as possible. the traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. example layout figures 14a, 14b, 14c and 14d show the schematic and layout of an evaluation board. the layout demonstrates the proper use of decoupling capacitors and ground plane with a 2-layer printed circuit board. digital interface the a/d converter is designed to interface with micropro- cessors as a memory mapped device. the cs and rd control inputs are common to all peripheral memory interfacing. a separate convst is used to initiate a con- version. internal clock the a/d converter has an internal clock that eliminates the need for synchronization between the external clock and the cs and rd signals found in other adcs. the internal clock is factory trimmed to achieve a typical conversion time of 1.8 m s, and a maximum conversion time over the full operating temperature range of 2.2 m s. no external adjustments are required. the guaranteed maximum acquisition time is 400ns. in addition, a throughput time of 2.5 m s and a minimum sampling rate of 400ksps is guaranteed. power shutdown the ltc1416 provides two power shutdown modesnap mode and sleep mode to save power during inactive periods. the nap mode reduces the power by 95% and leaves only the digital logic and reference powered up. the wake-up time from nap to active is 200ns. in sleep mode the reference is shut down and only a small current of 120 m a remains. wake-up time from sleep mode is much slower since the reference circuit must power up and settle to 0.005% for full 14-bit accuracy. sleep mode wake-up time is dependent on the value of the capacitor connected to the refcomp (pin 4). the wake-up time is 20ms with the recommended 22 m f capacitor. 1416 f13 10 m f 10 m f analog input circuitry 5 4 2 26 28 27 14 1 22 m f digital system a in + agnd refcomp v ss av dd ltc1416 dv dd dgnd a in +
16 ltc1416 applicatio n s i n for m atio n wu u u + +v in gnd a + a agnd dgnd v cc v cc v cc v ss v ref jp4 v logic r14 20 w u4 ltc1416 b[00:13] u5 74hc574 u6 74hc574 98 hc14 u7d j6-13 j6-14 j6-11 j6-12 j6-9 j6-10 j6-7 j6-8 j6-5 j6-6 j6-3 j6-4 j6-1 j6-2 j6-15 j6-16 j6-17 j6-18 d13 d00 d01 d02 d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 d13 d13 rdy d00 d01 d02 d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 d13 d13 rdy dgnd dgnd led jp1 d00 d01 d02 d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 d13 d00 d01 d02 d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 d13 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d[00:13] r0, 1.2k r1, 1.2k r2, 1.2k r3, 1.2k r4, 1.2k r5, 1.2k r6, 1.2k r8, 1.2k r7, 1.2k r9, 1.2k r10, 1.2k r11, 1.2k r12, 1.2k r13, 1.2k header 18-pin 11 10 hc14 r21 1k v logic v cc gnd d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d12 d11 d10 d09 d08 d07 d06 d00 d01 d02 d03 d04 d05 d13 19 18 17 16 15 14 13 12 19 18 17 16 15 14 13 12 q0 q1 q2 q3 q4 q5 q6 q7 q0 q1 q2 q3 q4 q5 q6 q7 0e 0e data ready notes: unless otherwise specified all resistor values in ohms, 5% v cc v ss clk j7 v in u2 lt1121-5 d15 ss12 r17 10k r18 10k r19 51 w r16 51 w r15 51 w jp5c rd shdn cs hc14 hc14 c11 1000pf c8 1 m f 10v c13 22 m f 10 v c9 10 f 10v c6 15pf c5 10 f 10v c2 22 f 10v c10 10 f 10v c1 22 f 10v c12 0.1 f c14 0.1 f gnd tabgnd 1 24 3 c4 0.1 m f c3 0.1 m f u3 lt1363 v v + 2 3 1 23 4 6 7 8 1 4 j3 7v to 15v j4 jp2 j5 jp3 v out v out j2 1 2 3 4 25 24 23 22 21 28 27 26 5 14 6 7 8 9 10 11 12 13 15 16 17 18 19 20 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 b00 b01 b02 b03 b04 b05 b13 b12 b11 b10 b09 b08 b07 b06 1 11 2 3 4 5 6 7 8 9 1 11 2 3 4 5 6 7 8 9 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a in + a in v ref refcomp busy cs convst rd shdn av dd dv dd v ss agnd dgnd jp5b jp5a r20 1m v logic 14 7 13 12 u7f hc14 + + v ss j1 7v to 15v d14 ss12 ? in 2 5 1 u1 79l05 + 1416 f14a v in v out gnd u7g hc14 u7b u7a u7e c15 0.1 f 56 hc14 u7c figure 14a. suggested evaluation circuit schematic
17 ltc1416 applicatio n s i n for m atio n wu u u figure 14b. suggested evaluation circuit board component side silkscreen figure 14c. suggested evaluation circuit board component side layout figure 14d. suggested evaluation circuit board solder side layout t 3 shdn convst 1416 f15b figure 15b. shdn to convst wake-up timing t 3 cs shdn 1416 f15a figure 15a. cs to shdn timing
18 ltc1416 applicatio n s i n for m atio n wu u u shutdown is controlled by pin 21 (shdn), the adc is in shutdown when it is low. the shutdown mode is selected with pin 20 (cs), low selects nap. timing and control conversion start and data read operations are controlled by three digital inputs: convst, cs and rd. a logic 0 applied to the convst pin will start a conversion after the adc has been selected (i.e., cs is low). once initiated, it cannot be restarted until the conversion is complete. converter status is indicated by the busy output. busy is low during a conversion. figures 16 through 21 show several different modes of operation. in modes 1a and 1b (figures 17 and 18) cs and rd are both tied low. the falling edge of convst starts the conversion. the data outputs are always enabled and data can be latched with the busy rising edge. mode 1a shows operation with a narrow logic low convst pulse. mode 1b shows a narrow logic high convst pulse. in mode 2 (figure 19) cs is tied low. the falling edge of convst signal again starts the conversion. data outputs are in three-state until read by the mpu with the rd signal. mode 2 can be used for operation with a shared mpu data bus. in slow memory and rom modes (figures 20 and 21), cs is tied low and convst and rd are tied together. the mpu figure 16. cs to convst setup timing t 2 t 1 cs convst rd 1416 f16 data n db13 to db0 data (n + 1) db13 to db0 data (n ?1) db13 to db0 convst cs = rd = 0 busy 1416 f17 t 5 t conv t 6 t 8 t 7 data (sample n) (convst = ) figure 17. mode 1a. convst starts a conversion. data outputs always enabled starts the conversion and reads the output with the rd signal. conversions are started by the mpu or dsp (no external sample clock). in slow memory mode the processor applies a logic low to rd (= convst), starting the conversion. busy goes low, forcing the processor into a wait state. the previous conversion result appears on the data outputs. when the conversion is complete, the new conversion results appear on the data outputs; busy goes high releasing the processor, and the processor takes rd (= convst) back high and reads the new conversion data. in rom mode, the processor takes rd (= convst) low, starting a conversion and reading the previous conversion result. after the conversion is complete, the processor can read the new result and initiate another conversion.
19 ltc1416 applicatio n s i n for m atio n wu u u data (n ?1) db13 to db0 convst busy 1416 f18 t conv t 6 t 13 t 7 cs = rd = 0 data n db13 to db0 data (n + 1) db13 to db0 data t 5 t 6 t 6 t 8 figure 18. mode 1b. convst starts a conversion. data outputs always enabled (convst = ) rd = convst cs = 0 busy 1416 f20 t conv (sample n) t 6 data (n ?1) db13 to db0 data data n db13 to db0 data (n + 1) db13 to db0 data n db13 to db0 t 11 t 8 t 10 t 7 figure 20. slow memory mode timing figure 19. mode 2. convst starts a conversion. data is read by rd convst cs = 0 busy 1416 f19 t 5 t conv (sample n) t 8 t 13 t 6 t 9 t 12 data n db13 to db0 t 11 t 10 rd data information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20 ltc1416 1416f lt/tp 0598 4k ? printed in usa ? linear technology corporation 1997 applicatio n s i n for m atio n wu u u figure 21. rom mode timing rd = convst busy cs = 0 1416 f21 t conv (sample n) t 6 data (n ?1) db13 to db0 data data n db13 to db0 t 10 t 11 t 8 g28 ssop 0694 0.005 ?0.009 (0.13 ?0.22) 0 ?8 0.022 ?0.037 (0.55 ?0.95) 0.205 ?0.212** (5.20 ?5.38) 0.301 ?0.311 (7.65 ?7.90) 1234 5 6 7 8 9 10 11 12 14 13 0.397 ?0.407* (10.07 ?10.33) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 0.068 ?0.078 (1.73 ?1.99) 0.002 ?0.008 (0.05 ?0.21) 0.0256 (0.65) bsc 0.010 ?0.015 (0.25 ?0.38) dimensions do not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimensions do not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** g package 28-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) u package d e sc r i pti o dimensions in inches (millimeters) unless otherwise noted. part number description comments ltc1278/ltc1279 single supply, 12-bit, 500ksps/600ksps adcs low power, 5v or 5v supply ltc1400 high speed serial 12-bit adc 400ksps, complete with v ref , clk, sample-and-hold in so-8 ltc1409 low power, 12-bit, 800ksps sampling adc best dynamic performance, f sample 800ksps, 80mw dissipation ltc1410 12-bit, 1.25msps sampling adc with shutdown best dynamic performance, thd = 84db and sinad = 71db at nyquist ltc1412 12-bit, 3msps sampling adc best dynamic performance, sinad = 72db at nyquist ltc1415 single 5v, 12-bit, 1.25msps adc single supply, 55mw dissipation ltc1418 14-bit, 200ksps sampling adc 16mw dissipation, serial and parallel outputs ltc1419 14-bit, 800ksps sampling adc with shutdown 81.5db sinad, 150mw from 5v supplies ltc1604 16-bit, 333ksps sampling adc 2.5v input, sinad = 90db, thd = 100db ltc1605 single 5v, 16-bit, 100ksps adc low power, 10v inputs related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com

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